In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected and developed, it is indelibly formed in the coating.
One important aspect of producing an integrated circuit involves the isolation of devices that are built on a semiconductor substrate of a wafer. For instance, isolation becomes extremely important in integrated circuit technology as many hundreds of thousands of devices are produced in a single chip. Improper isolation among transistors may cause current leakages, which can consume significant power for the entire chip. Further, improper isolation can lead to increased noise among devices on the chip.
One known way of isolating devices built on a semiconductor chip involves local oxidation of silicon (LOCOS). LOCOS involves growing silicon dioxide by heating an exposed area of silicon (or silicon covered with a thin layer of silicon dioxide) in an oxygen containing ambient. Prior to LOCOS growth, a wafer will normally be covered with an inert layer of material, such as silicon nitride (Si3N4), and the nitride layer is patterned to expose the areas selected for LOCOS formation. The localized regions of oxide are then grown in the exposed areas, and the silicon nitride layer is then removed.
Another way of isolating devices built on a semiconductor chip is to form isolation regions between neighboring devices. For instance, using a shallow trench isolation technique, shallow trenches are formed between devices on the semiconductor chip so that a dielectric layer such as silicon oxide may be formed therein to electrically isolate adjacent devices. In order to produce the shallow trenches, a barrier oxide layer is typically formed over a semiconductor substrate, and a silicon nitride layer is formed over the barrier oxide layer. Next, a photoresist is patterned over the silicon nitride layer to serve as a mask when forming the shallow trench. Using the photoresist, the shallow trench is formed through the layers into the semiconductor substrate and is filled with the dielectric material. The photoresist and silicon oxide layer are subsequently removed using conventional techniques.
During any lithographic/etching process such as that involved in forming the shallow trench isolation regions, it is extremely important to control critical dimensions (CDs) such as linewidth and spacing of the photoresist. Unfortunately, the use of highly reflective materials such as metal silicides in photolithography has lead to difficulties in maintaining tight CD control. In particular, undesired and nonuniform reflections from these underlying materials during the photoresist patterning process often causes the resulting photoresist patterns to be distorted. Because the photoresist patterns are used as a mask in forming the shallow isolation trenches, such distortions have a corresponding negative impact on the CD control of these trenches.
Distortion in the photoresist are further created during passage of reflected light through a silicon nitride layer Si3N4 which is used as a hardmask for shallow trench isolation etching. As is conventional, the hardmask serves to provide an additional mask layer for forming the shallow trenches in the event the softer photoresist material becomes eroded prior to or during the isolation trench forming steps. During manufacturing of the semiconductor chip, however, normal fluctuations in the thickness of the hardmask cause a wide range of varying reflectivity characteristics across the silicon nitride layer. As a result, maintaining tight CD control of the photoresist pattern and ultimately the isolation trenches is difficult.
A known method for reducing the negative effects resulting from the reflective materials used in forming a semiconductor chip includes the use of anti-reflective coatings (ARCs). For example, one type of ARC is a polymer film that is formed between the photoresist and the semiconductor substrate. The ARC serves to absorb most of the radiation that penetrates the resist (70–85%) thereby reducing the negative effects stemming from the underlying reflective materials during photoresist patterning. Unfortunately, use of an ARC adds significant drawbacks with respect to process complexity. For instance, in order to utilize an organic or inorganic ARC, the process of manufacturing the semiconductor chip must include a process step for depositing the ARC material, and also a step for prebaking the ARC before spinning the photoresist.
Accordingly, there exists a need in the art for a method of forming a resist pattern for shallow trench isolation which overcomes the drawbacks described above and others.